Add Makefile and testgenerator to run vhdl files

1 files changed, 30 insertions, 0 deletions

diff --git a/sem6/dig/m2/Makefile b/sem6/dig/m2/Makefile
new file mode 100644
index 0000000..2731d67
--- /dev/null
+++ b/sem6/dig/m2/Makefile
@@ -0,0 +1,30 @@
+
+INPUTFILES=nor_gate
+
+all: $(INPUTFILES)
+
+.PHONY: all clean
+
+%.o: %.vhdl
+	ghdl -a $^
+
+$(INPUTFILES): %: %.o
+	ghdl -e $@
+
+test_%.vhdl: %.vhdl generate_test_file.py
+	./generate_test_file.py $< $@
+
+test_$(INPUTFILES): %: %.o
+	ghdl -e $@
+
+run_%: %
+	ghdl -r $^
+
+sim_%: test_% %
+	-./$< --vcd=out.vcd
+
+clean:
+	ghdl --clean
+	rm -f work*.cf
+	rm -f test_*.vhdl
+