diff options
| -rw-r--r-- | sem6/dig/m2/Makefile | 30 | ||||
| -rwxr-xr-x | sem6/dig/m2/generate_test_file.py | 76 | ||||
| -rw-r--r-- | sem6/dig/m2/nor_gate.vhdl | 15 | ||||
| -rw-r--r-- | sem6/dig/m2/noter.md | 55 |
4 files changed, 176 insertions, 0 deletions
diff --git a/sem6/dig/m2/Makefile b/sem6/dig/m2/Makefile new file mode 100644 index 0000000..2731d67 --- /dev/null +++ b/sem6/dig/m2/Makefile @@ -0,0 +1,30 @@ + +INPUTFILES=nor_gate + +all: $(INPUTFILES) + +.PHONY: all clean + +%.o: %.vhdl + ghdl -a $^ + +$(INPUTFILES): %: %.o + ghdl -e $@ + +test_%.vhdl: %.vhdl generate_test_file.py + ./generate_test_file.py $< $@ + +test_$(INPUTFILES): %: %.o + ghdl -e $@ + +run_%: % + ghdl -r $^ + +sim_%: test_% % + -./$< --vcd=out.vcd + +clean: + ghdl --clean + rm -f work*.cf + rm -f test_*.vhdl + diff --git a/sem6/dig/m2/generate_test_file.py b/sem6/dig/m2/generate_test_file.py new file mode 100755 index 0000000..c450f02 --- /dev/null +++ b/sem6/dig/m2/generate_test_file.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python +import json +import argparse +import re +import sys +import os +import jinja2 as j2 + +test_define_re = re.compile("TEST_START(.*)TEST_STOP") + +parser = argparse.ArgumentParser() +parser.add_argument("file", help="vhdl file to read from") +parser.add_argument("output", help="vhdl file to save to") + +args = parser.parse_args() + +def load_file_def(fname): + filecontent = "" + with open(fname, "r") as f: + filecontent = f.read() + + groups = test_define_re.search(filecontent).groups() + if groups: + return json.loads(groups[0]) + else: + print("No def in file", f=sys.stderr) + +test_def = load_file_def(args.file) +name = os.path.splitext(args.file)[0] + +# Generate test file, by running all inputs TODO make this more configurable + +testbed_template = j2.Template(""" +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity test_{{name}} is +end test_{{name}}; + +architecture behavior of test_{{name}} is + component {{name}} is + port ( + {% for input in inputs %}{{input}}: in std_logic; + {% endfor %}{% for output in outputs %}{{output}}: out std_logic{% if not loop.last %};{% endif %} + {% endfor %}); + end component; + signal input : std_logic_vector({{ num_inputs - 1 }} downto 0); + signal output : std_logic_vector({{ num_inputs - 1 }} downto 0); +begin + uut: {{name}} port map ( + {% for input in inputs %}{{input}} => input({{loop.index-1}}), + {% endfor %}{% for output in outputs %}{{output}} => output({{loop.index-1}}){% if not loop.last %},{% endif %}{% endfor %} + ); + + stim_proc: process + begin + {% for test in testin %} + input <= "{{test}}"; wait for 1 fs; + {% endfor %} + wait; + end process; +end; +""") + +render = testbed_template.render( + name=name, + inputs=test_def["inputs"], + num_inputs=len(test_def["inputs"]), + outputs=test_def["outputs"], + num_outputs=len(test_def["outputs"]), + testin=test_def["testin"] + ) + +with open(args.output, "w") as f: + print(render, file=f) + diff --git a/sem6/dig/m2/nor_gate.vhdl b/sem6/dig/m2/nor_gate.vhdl new file mode 100644 index 0000000..7524a05 --- /dev/null +++ b/sem6/dig/m2/nor_gate.vhdl @@ -0,0 +1,15 @@ +-- TEST_START{"inputs": ["a", "b"], "outputs": ["o"], "testin": ["00", "10", "01", "11"]}TEST_STOP +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.all; + +ENTITY nor_gate IS + PORT( + a: IN STD_LOGIC; + b: IN STD_LOGIC; + o: OUT STD_LOGIC); +END nor_gate; + +ARCHITECTURE sample OF nor_gate IS +BEGIN + o <= a NOR b; +END sample; diff --git a/sem6/dig/m2/noter.md b/sem6/dig/m2/noter.md new file mode 100644 index 0000000..9a59572 --- /dev/null +++ b/sem6/dig/m2/noter.md @@ -0,0 +1,55 @@ +# Noter til digital design m2 + +Configurable element +: I think the same as logic block + +Island type architecture: +: How to interconnect the configurable busses between Logic blocks +: This can be done as either DISJOINT, UNIVERSAL or WILTON + +## VHDL + +Her bruger man rigtig meget `ENTITY` i stedet for verilog module. + +```vhdl +ENTITY nor_gate IS + PORT ( + x: IN STD_LOGIC; + y: IN STD_LOGIC; + z: OUT STD_LOGIC; + ); +END nor_gate; +``` + +Here semicolon is a seperator. +`STD_LOGIC` is for boolean values. + +`Architecture implements the ENTITY`. + +```vhdl +ARCHITECTURE sample OF nor_gate IS +BEGIN + z <= x NOR y; +END sample; +``` + +`INOUT` can be used have an input and output, so *bi-directional*. + +Different types, these come with IEEE libraries. + +- `STD_LOGIC`: boolean (`1`, `0`, `Z`), with Z being high impedance + + THere are more options here but chose were not covered. +- `STD_LOGIC_VECTOR`: Sequence of values. + +``` +STD_LOGIC_VECTOR(7 DOWNTO 0): for MSB +``` + +`SIGNAL` is a wire inside the design. + +``` +SIGNAL x: STD_LOGIC +``` + +Okay so `COMPONENTS` are the equivilent of functions. |