Changes to dig exercises

2 files changed, 13 insertions, 4 deletions

diff --git a/sem6/dig/m5/ex2.vhdl b/sem6/dig/m5/ex2.vhdl
index dc295c1..bed016a 100644
--- a/sem6/dig/m5/ex2.vhdl
+++ b/sem6/dig/m5/ex2.vhdl
@@ -1,4 +1,4 @@
--- TEST_START{"inputs": [], "outputs": ["output,23,0"], "clk": "clk", "testcount": 100}TEST_STOP
+-- TEST_START{"inputs": [], "outputs": ["output,23,0", "leds,7,0"], "clk": "clk", "testcount": 1000}TEST_STOP
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -6,14 +6,18 @@ use ieee.numeric_std.all;
 entity ex2 is
     port (
         clk: in std_logic;
-        output: out std_logic_vector(23 downto 0)
+        output: out std_logic_vector(23 downto 0);
+        leds: out std_logic_vector(7 downto 0)
     );
 end ex2;
 
 architecture impl of ex2 is
     signal value: unsigned(23 downto 0) := "000000000000000000000000";
+    signal output_int: std_logic_vector(23 downto 0);
 begin
-    output <= std_logic_vector(value);
+    output_int <= std_logic_vector(value);
+    output <= output_int;
+    leds <= output_int(7 downto 0);
 
     process (clk)
     begin
@@ -23,3 +27,8 @@ begin
     end process;
 
 end impl;
+
+-- The first bit of the leds blinks in the same frequency as clock.
+-- The second bit will have a full cycle in two first bit cycles, so clock / 2.
+-- The third bit will have clock / 2 / 2 og clock / (2 * 2).
+-- The general form is clock / (2 ^ n) where n is the bit index starting at 0.
diff --git a/sem6/dig/m5/ex3.vhdl b/sem6/dig/m5/ex3.vhdl
index 57465c4..d3d8853 100644
--- a/sem6/dig/m5/ex3.vhdl
+++ b/sem6/dig/m5/ex3.vhdl
@@ -1,4 +1,4 @@
--- TEST_START{"inputs": [], "outputs": ["output,6,0"], "clk": "clk", "testcount": 100}TEST_STOP
+-- TEST_START{"inputs": [], "outputs": ["output,6,0"], "clk": "clk", "testcount": 1000}TEST_STOP
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;