Add Makefile and testgenerator to run vhdl files

1 files changed, 15 insertions, 0 deletions

diff --git a/sem6/dig/m2/nor_gate.vhdl b/sem6/dig/m2/nor_gate.vhdl
new file mode 100644
index 0000000..7524a05
--- /dev/null
+++ b/sem6/dig/m2/nor_gate.vhdl
@@ -0,0 +1,15 @@
+-- TEST_START{"inputs": ["a", "b"], "outputs": ["o"], "testin": ["00", "10", "01", "11"]}TEST_STOP
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+
+ENTITY nor_gate IS
+    PORT(
+            a: IN STD_LOGIC;
+            b: IN STD_LOGIC;
+            o: OUT STD_LOGIC);
+END nor_gate;
+
+ARCHITECTURE sample OF nor_gate IS
+BEGIN
+    o <= a NOR b;
+END sample;