Add many more solutions and notes

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diff --git a/sem6/dig/m2/ex3.vhdl b/sem6/dig/m2/ex3.vhdl
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+-- TEST_START{"inputs": ["a", "b"], "outputs": ["o"], "testin": ["00", "01", "10", "11"]}TEST_STOP
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+
+ENTITY ex3 IS
+    PORT(
+        a: IN STD_LOGIC;
+        b: IN STD_LOGIC;
+        o: OUT STD_LOGIC);
+END ex3;
+
+ARCHITECTURE impl OF ex3 IS
+BEGIN
+    o <= a and b;
+END impl;