Added execise 2 for m4

3 files changed, 48 insertions, 3 deletions

diff --git a/sem6/dig/generate_test_file.py b/sem6/dig/generate_test_file.py
index d16164d..ee82836 100755
--- a/sem6/dig/generate_test_file.py
+++ b/sem6/dig/generate_test_file.py
@@ -47,6 +47,9 @@ architecture behavior of test_{name} is
 
     # Generate PORT section
     first = True
+    if "clk" in td:
+        tof(f"{td['clk']}: IN STD_LOGIC")
+        first = False
     for i in td["inputs"]:
         if not first:
             tof(";\n")
@@ -70,6 +73,8 @@ architecture behavior of test_{name} is
     tof(");\nend component;\n");
 
     # Define signals
+    if "clk" in td:
+        tof(f"signal in_{td['clk']}: STD_LOGIC;\n")
     for i in td["inputs"]:
         args = i.split(",")
         if len(args) > 1:
@@ -88,6 +93,9 @@ architecture behavior of test_{name} is
         uut: {name} port map(\n""")
 
     first = True
+    if "clk" in td:
+        tof(f"{td['clk']} => in_{td['clk']}")
+        first = False
     for i in td["inputs"]:
         if not first:
             tof(",\n")
@@ -102,14 +110,23 @@ architecture behavior of test_{name} is
         tof(f"{args[0]} => out_{args[0]}")
     tof(");\n\nstim_proc: process\nbegin\n")
 
-    for t in td["testin"]:
+    def wait():
+        tof(f"wait for {td.get('teststep', 1)} fs;")
+
+    for tindex, t in enumerate(td["testin"]):
+        # Add clock
+        if "clk" in td:
+            tof(f"in_{td['clk']} <= '0';")
         for index, i in enumerate(td["inputs"]):
             args = i.split(",")
             if len(args) > 1:
                 tof(f"in_{args[0]} <= \"{t[index]}\";")
             else:
                 tof(f"in_{args[0]} <= '{t[index]}';")
-        tof(f"wait for {td.get('teststep', 1)} fs;")
+        wait()
+        if "clk" in td:
+            tof(f"in_{td['clk']} <= '1';")
+        wait()
     tof("wait;\nend process;\nend;")
 
 
diff --git a/sem6/dig/m4/Makefile b/sem6/dig/m4/Makefile
index 0b35d0c..53c83b2 100644
--- a/sem6/dig/m4/Makefile
+++ b/sem6/dig/m4/Makefile
@@ -1,4 +1,4 @@
 
-INPUTFILES=ex1 dflip
+INPUTFILES=ex1 ex2
 
 include ../common.mk
diff --git a/sem6/dig/m4/ex2.vhdl b/sem6/dig/m4/ex2.vhdl
new file mode 100644
index 0000000..76883ad
--- /dev/null
+++ b/sem6/dig/m4/ex2.vhdl
@@ -0,0 +1,28 @@
+-- TEST_START{"inputs": ["sw0"], "outputs": ["o,3,0"], "clk": "bt0", "testin": "000111001001"}TEST_STOP
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex2 is
+    port (
+        sw0: in std_logic;
+        bt0: in std_logic;
+        o: out std_logic_vector(3 downto 0)
+    );
+end ex2;
+
+architecture impl of ex2 is
+    signal state: std_logic_vector(3 downto 0) := "0000";
+    signal next_state: std_logic_vector(3 downto 0) := "0000";
+begin
+    -- Implement shifting
+    next_state(3 downto 1) <= state(2 downto 0);
+    next_state(0) <= sw0;
+    o <= state;
+
+    process (bt0)
+    begin
+        if (bt0'event and bt0 = '1') then
+            state <= next_state;
+        end if;
+    end process;
+end impl;