diff options
author | Julian T <julian@jtle.dk> | 2021-02-22 14:06:19 +0100 |
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committer | Julian T <julian@jtle.dk> | 2021-02-22 14:06:19 +0100 |
commit | 29d49ef6cf9f84e922ef91a2921129ecc97cbf55 (patch) | |
tree | 712b5e011faf303376e9053d2f747218095150db | |
parent | 4377c42e7c6a46f5eeaae2f1bcf08a909caf35af (diff) |
Working exercise for m4
-rw-r--r-- | sem6/dig/m4/dflip.vhdl | 26 | ||||
-rw-r--r-- | sem6/dig/m4/ex1.vhdl | 52 |
2 files changed, 10 insertions, 68 deletions
diff --git a/sem6/dig/m4/dflip.vhdl b/sem6/dig/m4/dflip.vhdl deleted file mode 100644 index 5f722d3..0000000 --- a/sem6/dig/m4/dflip.vhdl +++ /dev/null @@ -1,26 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.all; - -ENTITY dflip IS - PORT( - d: IN STD_LOGIC; - clk: IN STD_LOGIC; - q: OUT STD_LOGIC; - nq: OUT STD_LOGIC - ); -END dflip; - -ARCHITECTURE impl OF dflip IS - SIGNAL qi : STD_LOGIC; -BEGIN - nq <= NOT qi; - q <= qi; - PROCESS (clk) - BEGIN - -- Check if high edge - if (clk'event and clk = '1') then - qi <= d; - end if; - END PROCESS; -END IMPL; - diff --git a/sem6/dig/m4/ex1.vhdl b/sem6/dig/m4/ex1.vhdl index 159dfff..326994a 100644 --- a/sem6/dig/m4/ex1.vhdl +++ b/sem6/dig/m4/ex1.vhdl @@ -1,4 +1,4 @@ --- TEST_START{"inputs": ["clk"], "outputs": [],"teststep": 10, "testin": "101010101010101010101010101010"}TEST_STOP +-- TEST_START{"inputs": ["clk"], "outputs": [],"teststep": 10, "testin": "0101010101010101010101010101010"}TEST_STOP LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; @@ -9,51 +9,19 @@ ENTITY ex1 IS END ex1; ARCHITECTURE impl OF ex1 IS - SIGNAL seed : STD_LOGIC := '1'; - SIGNAL a : STD_LOGIC := '0'; - SIGNAL first_out : STD_LOGIC := '0'; - SIGNAL b : STD_LOGIC := '0'; - SIGNAL c : STD_LOGIC := '0'; - SIGNAL d : STD_LOGIC := '0'; - SIGNAL lp : STD_LOGIC := '0'; + SIGNAL state: std_logic_vector(3 downto 0) := "0001"; + signal next_state: std_logic_vector(3 downto 0) := "0000"; -BEGIN - lp <= c XOR d; - a <= seed OR first_out; - - flip1 : ENTITY work.dflip - PORT MAP ( - d => lp, - q => first_out, - clk => clk - ); - - flip2 : ENTITY work.dflip - PORT MAP ( - d => a, - q => b, - clk => clk - ); - - flip3 : ENTITY work.dflip - PORT MAP ( - d => b, - q => c, - clk => clk - ); - - flip4 : ENTITY work.dflip - PORT MAP ( - d => c, - q => d, - clk => clk - ); +begin + -- First program the nextstate logic + next_state(3 downto 1) <= state(2 downto 0); + next_state(0) <= state(2) xor state(3); + -- Implement latching on clock process (clk) begin - if (clk = '0' AND seed = '1') then - seed <= '0'; + if (clk'event and clk = '1') then + state <= next_state; end if; end process; - END impl; |