diff options
Diffstat (limited to 'sem6/dig/m2')
| -rw-r--r-- | sem6/dig/m2/Makefile | 2 | ||||
| -rw-r--r-- | sem6/dig/m2/ex1.vhdl | 23 | ||||
| -rw-r--r-- | sem6/dig/m2/ex3.vhdl | 15 | ||||
| -rw-r--r-- | sem6/dig/m2/noter.tex | 35 |
4 files changed, 74 insertions, 1 deletions
diff --git a/sem6/dig/m2/Makefile b/sem6/dig/m2/Makefile index 4f83294..2a4d25a 100644 --- a/sem6/dig/m2/Makefile +++ b/sem6/dig/m2/Makefile @@ -1,4 +1,4 @@ -INPUTFILES = nor_gate ex2 ex5 ex6 +INPUTFILES = nor_gate ex1 ex2 ex5 ex6 ex3 include ../common.mk diff --git a/sem6/dig/m2/ex1.vhdl b/sem6/dig/m2/ex1.vhdl new file mode 100644 index 0000000..33b187c --- /dev/null +++ b/sem6/dig/m2/ex1.vhdl @@ -0,0 +1,23 @@ +-- TEST_START{"inputs": ["sw1", "sw2", "sw3", "sw4"], "outputs": ["l1", "l2", "l3", "l4"], "testin": ["0000", "0001", "0101", "1101", "1010"]}TEST_STOP +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.all; + +ENTITY ex1 IS + PORT( + sw1: IN STD_LOGIC; + sw2: IN STD_LOGIC; + sw3: IN STD_LOGIC; + sw4: IN STD_LOGIC; + l1: OUT STD_LOGIC; + l2: OUT STD_LOGIC; + l3: OUT STD_LOGIC; + l4: OUT STD_LOGIC); +END ex1; + +ARCHITECTURE impl OF ex1 IS +BEGIN + l1 <= sw1; + l2 <= sw2; + l3 <= sw3; + l4 <= sw4; +END impl; diff --git a/sem6/dig/m2/ex3.vhdl b/sem6/dig/m2/ex3.vhdl new file mode 100644 index 0000000..8b3603a --- /dev/null +++ b/sem6/dig/m2/ex3.vhdl @@ -0,0 +1,15 @@ +-- TEST_START{"inputs": ["a", "b"], "outputs": ["o"], "testin": ["00", "01", "10", "11"]}TEST_STOP +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.all; + +ENTITY ex3 IS + PORT( + a: IN STD_LOGIC; + b: IN STD_LOGIC; + o: OUT STD_LOGIC); +END ex3; + +ARCHITECTURE impl OF ex3 IS +BEGIN + o <= a and b; +END impl; diff --git a/sem6/dig/m2/noter.tex b/sem6/dig/m2/noter.tex new file mode 100644 index 0000000..7a5c531 --- /dev/null +++ b/sem6/dig/m2/noter.tex @@ -0,0 +1,35 @@ +\title{Mininoter} + +Der findes har 3 forskellige typer: +\begin{itemize} + \item Island style eller array type som brugt af Xilinx + \item Hierachical brugt af Altera + \item Logarithmic hvilket er mere eksotisk +\end{itemize} + +Island style indeholder CE (Configurable Elements), IM (Interconnection Matrix) og CB (Connection Block). + +Hierachical har mere ting i hierachier i stedet for et grid. + +\section{VHDL} + +Architecture er en implementation af et design. +Et design kan have flere implementation hvilket er grunden til at man skal give den et unikt navn. + +\texttt{inout} er også en mulighed for pin type, og giver en bidirectional port. + +Forskellige værdier til \texttt{STD_LOGIC} og \texttt{STD_LOGIC_VECTOR}. + +\begin{itemize} + \item \texttt{1} -- forced high + \item \texttt{0} -- forced low + \item \texttt{Z} -- high impedance + \item \texttt{U} -- Uninitialized + \item \texttt{X} -- unknown, low impedance + \item \texttt{W} -- unknown (weak), low impedance + \item \texttt{L} -- weak 0 + \item \texttt{H} -- weak 1 + \item \texttt{-} -- wild card, don't care +\end{itemize} + +Port maps are used to compose modules at a higher level. |