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author | Julian T <julian@jtle.dk> | 2021-02-24 14:52:32 +0100 |
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committer | Julian T <julian@jtle.dk> | 2021-02-24 14:52:32 +0100 |
commit | bf931f790f2ad6f482df38b0f70e0bbd05c401d8 (patch) | |
tree | 35971041b5c9eff1b30d5d3cf1d46c86186e9fcd /sem6/dig/m4/ex3.vhdl | |
parent | 15e3da75a9e78c3ab9b03aa5e7c79b73cf1a2a47 (diff) |
Added assignment for m4 dig
Diffstat (limited to 'sem6/dig/m4/ex3.vhdl')
-rw-r--r-- | sem6/dig/m4/ex3.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/sem6/dig/m4/ex3.vhdl b/sem6/dig/m4/ex3.vhdl new file mode 100644 index 0000000..650d303 --- /dev/null +++ b/sem6/dig/m4/ex3.vhdl @@ -0,0 +1,20 @@ +-- TEST_START{"inputs": ["input,3,0", "write", "read"], "outputs": ["output,3,0"], "testin": [["0000", 0, 0], ["0000", 0, 1], ["1010", 1, 0], ["0000", 0, 1], ["1100", 1, 1], ["0011", 1, 1]]}TEST_STOP +library ieee; +use ieee.std_logic_1164.all; + +entity ex3 is + port ( + input: in std_logic_vector(3 downto 0); + write: in std_logic; + read: in std_logic; + output: out std_logic_vector(3 downto 0) + ); +end ex3; + +architecture impl of ex3 is + signal stuff: std_logic_vector(3 downto 0) := "0000"; +begin + output <= stuff when read = '1' else "ZZZZ"; + stuff <= input when write = '1' else stuff; + +end impl; |