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author | Julian T <julian@jtle.dk> | 2021-02-15 14:31:49 +0100 |
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committer | Julian T <julian@jtle.dk> | 2021-02-15 14:31:49 +0100 |
commit | 1e6f7a495318addcbb6bc5ae7465a2eb1d889acd (patch) | |
tree | a5a7a4940161a5814992e2775f4959ccb336f4d4 /sem6/dig/common.mk | |
parent | 1ea5fe8262ffe148c78ebc393ffe4886232a221e (diff) |
Add assignments for digital design
Diffstat (limited to 'sem6/dig/common.mk')
-rw-r--r-- | sem6/dig/common.mk | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/sem6/dig/common.mk b/sem6/dig/common.mk new file mode 100644 index 0000000..266511b --- /dev/null +++ b/sem6/dig/common.mk @@ -0,0 +1,29 @@ + + +all: $(INPUTFILES) + +.PHONY: all clean + +%.o: %.vhdl + ghdl -a $^ + +$(INPUTFILES): %: %.o + ghdl -e $@ + +test_%.vhdl: %.vhdl ../generate_test_file.py + ../generate_test_file.py $< $@ + +test_%: test_%.o + ghdl -e $@ + +run_%: % + ghdl -r $^ + +sim_%: test_% % + -./$< --vcd=out.vcd + +clean: + ghdl --clean + rm -f work*.cf + rm -f test_*.vhdl + |