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authorJulian T <julian@jtle.dk>2021-02-24 15:15:24 +0100
committerJulian T <julian@jtle.dk>2021-02-24 15:15:46 +0100
commit92876e17653abd7f46126d7419433c628d303cb8 (patch)
tree053fce8e2f16935756f3570f67112f26cfe6d11f
parentbf931f790f2ad6f482df38b0f70e0bbd05c401d8 (diff)
Add exercises for m5 dig
-rwxr-xr-xsem6/dig/generate_test_file.py7
-rw-r--r--sem6/dig/m5/Makefile4
-rw-r--r--sem6/dig/m5/ex2.vhdl25
-rw-r--r--sem6/dig/m5/ex3.vhdl29
4 files changed, 64 insertions, 1 deletions
diff --git a/sem6/dig/generate_test_file.py b/sem6/dig/generate_test_file.py
index 5a951f2..b97cbe6 100755
--- a/sem6/dig/generate_test_file.py
+++ b/sem6/dig/generate_test_file.py
@@ -113,7 +113,12 @@ architecture behavior of test_{name} is
def wait():
tof(f"wait for {td.get('teststep', 1)} fs;")
- for tindex, t in enumerate(td["testin"]):
+ if "testin" in td:
+ enum = enumerate(td["testin"])
+ else:
+ enum = enumerate([1] * td["testcount"])
+
+ for tindex, t in enum:
# Add clock
if "clk" in td:
tof(f"in_{td['clk']} <= '0';")
diff --git a/sem6/dig/m5/Makefile b/sem6/dig/m5/Makefile
new file mode 100644
index 0000000..379436c
--- /dev/null
+++ b/sem6/dig/m5/Makefile
@@ -0,0 +1,4 @@
+
+INPUTFILES=ex2 ex3
+
+include ../common.mk
diff --git a/sem6/dig/m5/ex2.vhdl b/sem6/dig/m5/ex2.vhdl
new file mode 100644
index 0000000..dc295c1
--- /dev/null
+++ b/sem6/dig/m5/ex2.vhdl
@@ -0,0 +1,25 @@
+-- TEST_START{"inputs": [], "outputs": ["output,23,0"], "clk": "clk", "testcount": 100}TEST_STOP
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ex2 is
+ port (
+ clk: in std_logic;
+ output: out std_logic_vector(23 downto 0)
+ );
+end ex2;
+
+architecture impl of ex2 is
+ signal value: unsigned(23 downto 0) := "000000000000000000000000";
+begin
+ output <= std_logic_vector(value);
+
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ value <= value + 1;
+ end if;
+ end process;
+
+end impl;
diff --git a/sem6/dig/m5/ex3.vhdl b/sem6/dig/m5/ex3.vhdl
new file mode 100644
index 0000000..57465c4
--- /dev/null
+++ b/sem6/dig/m5/ex3.vhdl
@@ -0,0 +1,29 @@
+-- TEST_START{"inputs": [], "outputs": ["output,6,0"], "clk": "clk", "testcount": 100}TEST_STOP
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ex3 is
+ port (
+ clk: in std_logic;
+ output: out std_logic_vector(6 downto 0)
+ );
+end ex3;
+
+architecture impl of ex3 is
+ signal value: unsigned(6 downto 0) := "0000000";
+begin
+ output <= std_logic_vector(value);
+
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (value = 59) then
+ value <= "0000000";
+ else
+ value <= value + 1;
+ end if;
+ end if;
+ end process;
+
+end impl;