From 92876e17653abd7f46126d7419433c628d303cb8 Mon Sep 17 00:00:00 2001 From: Julian T Date: Wed, 24 Feb 2021 15:15:24 +0100 Subject: Add exercises for m5 dig --- sem6/dig/m5/ex2.vhdl | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 sem6/dig/m5/ex2.vhdl (limited to 'sem6/dig/m5/ex2.vhdl') diff --git a/sem6/dig/m5/ex2.vhdl b/sem6/dig/m5/ex2.vhdl new file mode 100644 index 0000000..dc295c1 --- /dev/null +++ b/sem6/dig/m5/ex2.vhdl @@ -0,0 +1,25 @@ +-- TEST_START{"inputs": [], "outputs": ["output,23,0"], "clk": "clk", "testcount": 100}TEST_STOP +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ex2 is + port ( + clk: in std_logic; + output: out std_logic_vector(23 downto 0) + ); +end ex2; + +architecture impl of ex2 is + signal value: unsigned(23 downto 0) := "000000000000000000000000"; +begin + output <= std_logic_vector(value); + + process (clk) + begin + if (clk'event and clk = '1') then + value <= value + 1; + end if; + end process; + +end impl; -- cgit v1.2.3