From 15a334af05a1f53e37e3ee98021b0032035a7eee Mon Sep 17 00:00:00 2001
From: Julian T <julian@jtle.dk>
Date: Mon, 22 Feb 2021 16:05:21 +0100
Subject: Added execise 2 for m4

---
 sem6/dig/m4/ex2.vhdl | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 sem6/dig/m4/ex2.vhdl

(limited to 'sem6/dig/m4/ex2.vhdl')

diff --git a/sem6/dig/m4/ex2.vhdl b/sem6/dig/m4/ex2.vhdl
new file mode 100644
index 0000000..76883ad
--- /dev/null
+++ b/sem6/dig/m4/ex2.vhdl
@@ -0,0 +1,28 @@
+-- TEST_START{"inputs": ["sw0"], "outputs": ["o,3,0"], "clk": "bt0", "testin": "000111001001"}TEST_STOP
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ex2 is
+    port (
+        sw0: in std_logic;
+        bt0: in std_logic;
+        o: out std_logic_vector(3 downto 0)
+    );
+end ex2;
+
+architecture impl of ex2 is
+    signal state: std_logic_vector(3 downto 0) := "0000";
+    signal next_state: std_logic_vector(3 downto 0) := "0000";
+begin
+    -- Implement shifting
+    next_state(3 downto 1) <= state(2 downto 0);
+    next_state(0) <= sw0;
+    o <= state;
+
+    process (bt0)
+    begin
+        if (bt0'event and bt0 = '1') then
+            state <= next_state;
+        end if;
+    end process;
+end impl;
-- 
cgit v1.2.3