diff options
| -rwxr-xr-x | sem6/dig/generate_test_file.py | 2 | ||||
| -rw-r--r-- | sem6/dig/m4/Makefile | 2 | ||||
| -rw-r--r-- | sem6/dig/m4/ex3.vhdl | 20 |
3 files changed, 22 insertions, 2 deletions
diff --git a/sem6/dig/generate_test_file.py b/sem6/dig/generate_test_file.py index ee82836..5a951f2 100755 --- a/sem6/dig/generate_test_file.py +++ b/sem6/dig/generate_test_file.py @@ -123,8 +123,8 @@ architecture behavior of test_{name} is tof(f"in_{args[0]} <= \"{t[index]}\";") else: tof(f"in_{args[0]} <= '{t[index]}';") - wait() if "clk" in td: + wait() tof(f"in_{td['clk']} <= '1';") wait() tof("wait;\nend process;\nend;") diff --git a/sem6/dig/m4/Makefile b/sem6/dig/m4/Makefile index 53c83b2..1c04cdd 100644 --- a/sem6/dig/m4/Makefile +++ b/sem6/dig/m4/Makefile @@ -1,4 +1,4 @@ -INPUTFILES=ex1 ex2 +INPUTFILES=ex1 ex2 ex3 include ../common.mk diff --git a/sem6/dig/m4/ex3.vhdl b/sem6/dig/m4/ex3.vhdl new file mode 100644 index 0000000..650d303 --- /dev/null +++ b/sem6/dig/m4/ex3.vhdl @@ -0,0 +1,20 @@ +-- TEST_START{"inputs": ["input,3,0", "write", "read"], "outputs": ["output,3,0"], "testin": [["0000", 0, 0], ["0000", 0, 1], ["1010", 1, 0], ["0000", 0, 1], ["1100", 1, 1], ["0011", 1, 1]]}TEST_STOP +library ieee; +use ieee.std_logic_1164.all; + +entity ex3 is + port ( + input: in std_logic_vector(3 downto 0); + write: in std_logic; + read: in std_logic; + output: out std_logic_vector(3 downto 0) + ); +end ex3; + +architecture impl of ex3 is + signal stuff: std_logic_vector(3 downto 0) := "0000"; +begin + output <= stuff when read = '1' else "ZZZZ"; + stuff <= input when write = '1' else stuff; + +end impl; |