4 files changed, 90 insertions, 1 deletions
diff --git a/sem6/dig/generate_test_file.py b/sem6/dig/generate_test_file.py
index 42b8c8f..d16164d 100755
--- a/sem6/dig/generate_test_file.py
+++ b/sem6/dig/generate_test_file.py
@@ -109,7 +109,7 @@ architecture behavior of test_{name} is
                 tof(f"in_{args[0]} <= \"{t[index]}\";")
             else:
                 tof(f"in_{args[0]} <= '{t[index]}';")
-        tof("wait for 1 fs;")
+        tof(f"wait for {td.get('teststep', 1)} fs;")
     tof("wait;\nend process;\nend;")
 
 
diff --git a/sem6/dig/m4/Makefile b/sem6/dig/m4/Makefile
new file mode 100644
index 0000000..0b35d0c
--- /dev/null
+++ b/sem6/dig/m4/Makefile
@@ -0,0 +1,4 @@
+
+INPUTFILES=ex1 dflip
+
+include ../common.mk
diff --git a/sem6/dig/m4/dflip.vhdl b/sem6/dig/m4/dflip.vhdl
new file mode 100644
index 0000000..5f722d3
--- /dev/null
+++ b/sem6/dig/m4/dflip.vhdl
@@ -0,0 +1,26 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+
+ENTITY dflip IS
+    PORT(
+            d: IN STD_LOGIC;
+            clk: IN STD_LOGIC;
+            q: OUT STD_LOGIC;
+            nq: OUT STD_LOGIC
+        );
+END dflip;
+
+ARCHITECTURE impl OF dflip IS
+    SIGNAL qi : STD_LOGIC;
+BEGIN
+    nq <= NOT qi;
+    q <= qi;
+    PROCESS (clk)
+    BEGIN
+    -- Check if high edge
+        if (clk'event and clk = '1') then
+            qi <= d;
+        end if;
+    END PROCESS;
+END IMPL;
+
diff --git a/sem6/dig/m4/ex1.vhdl b/sem6/dig/m4/ex1.vhdl
new file mode 100644
index 0000000..159dfff
--- /dev/null
+++ b/sem6/dig/m4/ex1.vhdl
@@ -0,0 +1,59 @@
+-- TEST_START{"inputs": ["clk"], "outputs": [],"teststep": 10, "testin": "101010101010101010101010101010"}TEST_STOP
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.all;
+
+ENTITY ex1 IS
+    PORT(
+            clk: IN STD_LOGIC
+        );
+END ex1;
+
+ARCHITECTURE impl OF ex1 IS
+    SIGNAL seed : STD_LOGIC := '1';
+    SIGNAL a : STD_LOGIC := '0';
+    SIGNAL first_out : STD_LOGIC := '0';
+    SIGNAL b : STD_LOGIC := '0';
+    SIGNAL c : STD_LOGIC := '0';
+    SIGNAL d : STD_LOGIC := '0';
+    SIGNAL lp : STD_LOGIC := '0';
+
+BEGIN
+    lp <= c XOR d;
+    a <= seed OR first_out;
+
+    flip1 : ENTITY work.dflip
+    PORT MAP (
+                 d => lp,
+                 q => first_out,
+                 clk => clk
+             );
+
+    flip2 : ENTITY work.dflip
+    PORT MAP (
+                 d => a,
+                 q => b,
+                 clk => clk
+             );
+
+    flip3 : ENTITY work.dflip
+    PORT MAP (
+                 d => b,
+                 q => c,
+                 clk => clk
+             );
+
+    flip4 : ENTITY work.dflip
+    PORT MAP (
+                 d => c,
+                 q => d,
+                 clk => clk
+             );
+
+    process (clk)
+    begin
+        if (clk = '0' AND seed = '1') then
+            seed <= '0';
+        end if;
+    end process;
+
+END impl;